s6e2d5 series datasheet cypress semiconductor corporation 198 champion court san jose, ca 95134 408.943.2600 december 4, 2015 document no. 002 - 05034 rev. *a 1 september 16 , 2015 datasheet errata for s6e2d5 series 32 - bit arm? cortex? - m4f based microcontroller this document describes the errata for the s6e2d5 series 32 - bit arm? cortex? - m4f based microcontroller datasheet. compare this document to the devices data sheet for a complete functional description. contact your local cypress sales representative , if you have questions. part numbers affected part number s6e2d5 series page item description original document code: ds70 9 - 000 21 - 1v0 - e rev. 1.0 jun e 25, 2015 64 9. handling devices "sub crystal oscillator" should be a dded as indicated by the shading below. surface mount type size: more than 3.2 mm 1.5 mm load capacitance: approximately 6 pf to 7 pf when the standard setting (ccs/ccb=110011 10) load capacitance: approximately 4 pf to 7 pf when the low power setting (ccs/ccb=00000100) lead type load capacitance: approximately 6 pf to 7 pf when the standard setting (ccs/ccb=11001110) load capacitance: approximately 4 pf to 7 pf when t he low power setting (ccs/ccb=00000100)
errata document s6e2d5 series december 4, 2015 document no. 002 - 05034 rev. *a 2 page item description 92 14.3.1 current rating table 14 - 10 should be a dd ed as indicated by the shading below. t able 14 - 10 typical and maximum current consumption in deep standby stop mode, deep standby rtc mode and vbat parameter symbo l pin name conditions frequency (mhz) value unit remarks typ max power supply current iccvbat vbat rtc stop - 0.009 0.032 a *3, *4, *5 t a =+25c - 0.994 a *3, *4, *5 t a =+85c - 1.491 a *3, *4, *5 t a =+105c rtc *6 operation 1.0 1.636 a *3, *4 t a =+25c - 2.828 a *3, *4 t a =+85c - 4.242 a *3, *4 t a =+105c rtc *7 operation 0.7 1.153 a *3, * 4 t a =+25c - 2.277 a *3, *4 t a =+85c - 3.416 a *3, *4 t a =+105c *1: v cc =3.3 v *2: v cc =3.6 v *3: when all ports are fixed. *4: when lvd is off *5: when sub oscillation is off *6: when using the crystal oscillator of 32 khz (including the curr ent consumption of the oscillation circuit) when the standard setting (ccs/ccb=11001110) *7: when using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit) when the low power setting (ccs/ccb=00000100) 1 7 6 1 5. ordering information ordering information should be corrected as indicated by the shading below . (error) part n umber package s6e2d 5 5g0a g v20000 plastic ? lqfp (0.5 mm pitch ), 120 pin ( fpt - 120 p - m 21 ) s6e2d 5 5gjamv20000 s6e2d 5 5j0agv20000 plastic ? lqfp (0.5 mm pitch ), 176 pin ( fpt - 176p - m07 ) s6e2d 5 5g0agb 3 0000 plastic ? pfbga (0. 5 mm pitch ), 161 pin ( fdj161 ) s6e2d 5 5g0ag z 20000 plastic ? ex - l qfp (0.5 mm pitch ), 120 pin ( lem120 ) (correct) part n umber package s6e2d 5 5g0a g v20000 plastic ? lqfp (0.5 mm pitch ), 120 pin ( fpt - 120 p - m 21 ) s6e2d 5 5gjamv20000 s6e2d 5 5j0agv20000 plastic ? lqfp (0.5 mm pitch ), 176 pin ( fpt - 176p - m07 ) s6e2d 5 5g0agb 3 0000 plastic ? pfbga (0. 5 mm pitch ), 161 pin ( fdj161 ) s6e2d 5 5g0ag e 20000 plastic ? ex - l qfp (0.5 mm pitch ), 120 pin ( lem120 ) rev. 2 .0 september 16, 2015
errata document s6e2d5 series december 4, 2015 document no. 002 - 05034 rev. *a 3 page item description 11 2. features note should be added as indicated by the shading below. (error) gdc u nit controller for external graphics display accele rator for 2d block image transfer (blit) operations embedded sram video memory high - speed quad spi (serial peripheral interface for external memory extensions ) sdram interface for external memory extensions hbi (hyper bus interface) interface for external memory extensions maximum core system clock frequency : 160 mhz (correct) gdc u nit controller for external graphics display accelerator for 2d block image transfer (blit) operations embedded sram video memory high - speed quad spi (serial peripheral interfa ce for external memory extensions ) sdram interface for external memory extensions hbi (hyper bus interface) interface for external memory extensions maximum core system clock frequency : 160 mhz note : user can leverage the internal vram and external hyper ram as a graphics memory allowed to be written by gdc. 15 4. packages packages should be corrected as indicated by the shading below. (error) product n ame package s6e2d 5 5g0a s6e2d 5 5j0a s6e2d 5 5gja lqfp: fpt - 120p - m21 (0.5 mm pitch) ? ? - ? ? lqfp: fpt - 176p - m07 (0.5 mm pitch) - ? ? - pf bga: fdj161 (0.5 mm pitch) ? - - ex_lqfp(teqfp) : lem120 (0.5 mm pitch) ? ? ? : supported (correct) product n ame package s6e2d 5 5g0a s6e2d 5 5j0a s6e2d 5 5gja lqfp: fpt - 120p - m21 (0.5 mm pitch) ? ? - ? ? lqfp: fpt - 176p - m07 (0.5 mm pitch) - ? ? - fbga : fdj161 (0.5 mm pitch) ? - - ex_lqfp(teqfp) : lem120 (0.5 mm pitch) ? ? - - ? : supported ? : in development 16, 18 5. pin assignment signal name should be corrected as below. (error) ge_spcsx_0 (correct) g e_spcsx 0 (error) ge_hbcsx_0 (correct) ge_hbcsx 0 (error) ge_hbcsx_1 (correct) ge_hbcsx 1 21, 23, 48 6. pin descriptions signal name should be corrected as below. (error) ge_spcsx_0 (correct) ge_spcsx 0 (error) ge_hbcsx_0 (correct) ge_hbcsx 0 (er ror) ge_hbcsx_1 (correct) ge_hbcsx 1
errata document s6e2d5 series december 4, 2015 document no. 002 - 05034 rev. *a 4 page item description 67 10. block diagram signal name should be corrected as below. (error) ge_spcsx_0 (correct) ge_spcsx 0 (error) ge_hbcsx_0 /1 (correct) ge_hbcsx 0 /1 93 14.3 dc characteristics vflash memory standby current sh ould be corrected as indicated by the shading below. (error) parameter symbol pin name conditions value unit remarks min typ max vflash memory standby current i ccvflash vcc at standby - 15 25 a vflash memory r ead current at read - 9 14 ma 4 0mhz 13 20 80mhz vflash memory write/erase current at write/erase - 20 25 ma (correct) parameter symbol pin name conditions value unit remarks min typ max vflash memory standby current i ccvflash vcc at standby - 15 35 a vflash memor y r ead current at read - 9 14 ma 40mhz 13 20 80mhz vflash memory write/erase current at write/erase - 20 25 ma 162, 161, 162 14.4 ac characteristics signal name should be corrected as below. (error) ge_spcsx_0 (correct) ge_spcsx 0 (error ) ge_hbcsx_0 (correct) ge_hbcsx 0 (error) ge_hbcsx_1 (correct) ge_hbcsx 1
errata document s6e2d5 series december 4, 2015 document no. 002 - 05034 rev. *a 5 document history page document title: datasheet errata for s6e2d5 series 32 - bit arm? cortex? - m4f based microcontr oller document number: 002 - 05034 rev. ecn no. orig. of change description of change ** ? akih initial release *a 5037589 akih converted to cypress format all trademarks or registered trademarks referenced herein are the property of their resp ective owners. cypress semiconductor 198 champion court san jose, ca 95134 - 1709 phone: 408 - 943 - 2600 fax: 408 - 943 - 4730 http://www.cypress.com ? cypres s semiconductor corporation, 2015 . the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied i n a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, l ife saving, critical control or safety applications, unless pursuant to an exp ress written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the incl usion of cypress products in life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. this source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subject to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress here by grants to licensee a personal, non - exclusive, non - transferab le license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conj unction with a cypr ess integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or rep resentation of this source code except as specified above is prohibited without the express written permission of cypress. disc laimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes witho ut further notice to the materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authorize its products for use as critical components in lif e - supp ort systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress prod uct in a life - support systems application implies that the manufacturer assumes all risk of such use and in doi ng so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement.
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